1. Field of the Invention
The present invention relates to a semiconductor non-volatile memory, and particularly to an electrically writable and erasable semiconductor non-volatile memory (also called an EEPROM or Electrically Erasable and Programmable Read Only Memory). The present invention is particularly effective for a semiconductor non-volatile memory using a multi-value technique. Besides, the present invention relates to a semiconductor device including the semiconductor non-volatile memory.
2. Description of the Related Art
In the present specification, an electrically writable and erasable semiconductor non-volatile memory (EEPROM) indicates all semiconductor non-volatile memories in which electrical writing and electrical erasing are literally enabled, and includes, for example, a full function EEPROM and a flash memory in its category. Unless otherwise specified, the non-volatile memory and the semiconductor non-volatile memory are used to mean the EEPROM. Besides, the semiconductor device indicates all devices functioning by using semiconductor characteristics, and includes, for example, a microprocessor, an electro-optic device typified by a liquid crystal display device and an EL display device, and an electronic equipment incorporating a microprocessor or an electro-optic device in its category.
In recent years, an electrically writable and erasable semiconductor non-volatile memory (EEPROM), especially a flash memory has attracted attention as a promising candidate of a memory substituting for a magnetic disk or a DRAM. Above all, a so-called multi-value non-volatile memory each memory element of which stores data of three or higher values has attracted attention as a large capacity memory.
The non-volatile memory is divided into types, such as a NOR type, a NAND type, an AND type or a DINOR type, based on differences in their circuit structures and operation methods. As a memory element constituting the non-volatile memory, there is known a memory transistor including a floating gate, a memory transistor including a cluster layer, a memory transistor having MNOS (Metal-Nitride-Oxide-Semiconductor) structure or MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure, or the like.
In a conventional non-volatile memory, a hot electron injection method (called an HE injection system) and a charge injection method by FN tunnel current (called an FN current system) can be cited as a typical writing operation. In the HE injection system, a high control gate voltage and a high drain voltage are applied to a memory transistor to cause impact ionization, and a generated hot electron is drawn into a gate electrode side, so that an electric charge is injected into the memory transistor. On the other hand, in the FN current system, a high voltage is applied between a control gate electrode and a substrate to cause an FN tunnel current to flow, so that an electric charge is injected into a memory transistor.
In either case, in order to confirm that a threshold voltage after writing is within a predetermined range, verify writing is normally carried out. Especially, in a multi-value non-volatile memory, since it is necessary to control the threshold voltage after writing with high accuracy, the verify writing is indispensable. The verify writing is a method in which a small amount of charge injection and readout for confirming the threshold voltage are alternately carried out. This operation is repeated until the threshold voltage after writing falls within a predetermined range.
In the foregoing method of charge injection, there has been a problem that it is difficult to control the amount of charge injection with accuracy. This is because even in the case where the same operation voltage is applied to the memory transistor, if the charge storage amount of the memory transistor, that is, the threshold voltage is different, the charge injection speed is different.
Thus, naturally in memory transistors having different threshold voltages, even in the same memory transistor, the charge injection speed is changed as time elapses. For example, in the case where an electron is injected, a threshold voltage is increased, and an effective gate voltage seen from a channel region is decreased, so that the charge injection speed is decreased.
Further, if the charge injection speed fluctuates by a factor such as fluctuation in film quality of a tunnel oxide film, even if threshold voltages of memory transistors before writing are equal to each other, a difference gradually occurs in the charge storage amount. Then, a vicious circle occurs in which when a difference occurs in the threshold voltage, a charge injection amount further fluctuates.
The verify writing is one of methods for solving such problems. In the verify writing, since confirmation of the threshold voltage is carried out each time a small amount of charge is injected, it is not necessary to control the charge injection amount with high accuracy. However, in the verify writing, the operation of charge injection is divided into parts, and a readout operation is carried out between them, so that there is a problem that it essentially takes a period of time.
Incidentally, also in the verify writing, it is important to control the charge injection amount with accuracy. By controlling the charge injection amount with high accuracy, the number of times of division of the charge injection operation can be decreased, and so a verify writing time period can be shortened.
The present invention has been made in view of the above problems. An object of the present invention is to provide a non-volatile memory for carrying out a writing operation in which a charge injection amount can be controlled with high accuracy. Another object of the invention is to provide a non-volatile memory which realizes shortening of a verify writing time, and further, realizes substantial shortening of a writing time by a writing system without using a verify system. A still another object of the invention is to provide a semiconductor device including such a non-volatile memory.
As already described, in the conventional writing method, the charge injection speed depends on the charge storage amount of the memory transistor, and accordingly, depends on the threshold voltage. As a result, naturally in memory transistors of different states, even in the same memory transistor, the charge injection speed is changed as time elapses, and control of the charge injection amount has been difficult.
On the contrary, this means that in order to control the charge injection amount with high accuracy, a writing method is effective which has a charge injection speed independent on the charge storage amount of a memory transistor, that is, the threshold voltage. The inventor of the present invention has considered that the charge injection speed depends on the threshold voltage of the memory transistor since a control gate voltage of the memory transistor is directly controlled at the time of writing, and has devised, as a new writing method, a method of controlling a drain voltage and a drain current of the memory transistor.
That is, a non-volatile memory of the present invention is characterized in that a writing operation of a hot electron injection system is carried out by controlling a drain voltage and a drain current of a memory transistor. This writing method is characterized in that a control gate voltage is not directly controlled, but the control gate voltage is indirectly controlled so that the drain current becomes constant, and is characterized in that a charge injection speed does not depend on a threshold voltage.
In order to understand a writing operation in a non-volatile memory of the present invention, a simple circuit for carrying out writing into one memory element is cited as an example, and its operation method will be described. FIGS. 1A and 1B are used for the description.
As a memory element, various elements as shown in FIGS. 26A to 26D can be used (see embodiment 3 for more details). FIG. 26A shows a memory transistor in which a first insulating film 2602, a cluster layer 2603 constituted by semiconductor or conductor clusters 2604, a second insulating film 2605, and a control gate electrode 2606 are successively stacked on an active region 2601, and which is hereinafter referred to as a memory transistor having a cluster layer. FIG. 26D shows a memory transistor in which a first insulating film 2617, a floating gate electrode 2618 constituted by a semiconductor film or a conductive film, a second insulating film 2619, and a control gate electrode 2620 are successively stacked on an active region 2616, and which is hereinafter referred to as a memory transistor having a floating gate. FIGS. 26B and 26C show a memory transistor of MNOS structure and a memory transistor of MONOS structure, respectively.
Here, FIG. 1A shows an example of a circuit diagram using, as a memory element, the memory transistor having the cluster layer, the memory transistor of the MNOS structure, or the memory transistor of the MONOS structure, and FIG. 1B shows an example of a circuit diagram using the memory transistor having the floating gate. As symbolized by symbols of the respective memory elements, the memory transistor shown in FIG. 1A is characterized in that a region for storing an electric charge is spatially discrete, and the memory transistor shown in FIG. 1B is characterized in that a region for storing an electric charge is continuous. In both cases, the operation methods are quite identical to each other, and here, the description will be given with reference to FIG. 1A as an example.
The circuit diagram shown in FIG. 1A is composed of a memory transistor 101(a), a constant current source 102 for supplying an amount of current I, and an operational amplifier 103. The output of the operational amplifier 103 is connected to a control gate electrode of the memory transistor 101(a), the constant current source 102 is connected to a drain electrode, and a source electrode is grounded. The constant current source 102 and a voltage Vpgm are respectively connected to two input terminals of the operational amplifier 103.
The circuit shown in FIGS. 1A and 1B have negative feedback characteristics, and an operation is carried out in a state where two potentials inputted to the operational amplifier 103 are always equal to each other. As a result, in the circuit diagram shown in FIG. 1A, the memory transistor 101(a) operates in a state where a drain voltage is equal to Vpgm and a drain current is equal to I.
Actually, in the case where the drain voltage of the memory transistor 101(a) is higher than Vpgm, a positive current is outputted from the operational amplifier 103, and the control gate voltage of the memory transistor 101(a) is raised. As a result, the conductance of the memory transistor 101(a) is increased, and the drain voltage is lowered. To the contrary, in the case where the drain voltage of the memory transistor 101(a) is lower than Vpgm, a negative current is outputted from the operational amplifier 103, and the control gate voltage of the memory transistor 101(a) is lowered. As a result, it is understood that the conductance of the memory transistor 101(a) is decreased, and the drain voltage is raised.
In the present invention, as described above, the drain voltage and the drain current of the memory transistor are controlled, so that the writing operation of the HE injection system is carried out. Incidentally, Vpgm is called a writing voltage, and I is called a writing current.
When the foregoing writing method is used, and the drain voltage and the drain current are made constant, a channel region of the memory transistor has the same state independently of a charge storage amount of a floating gate. That is, the control gate voltage is shifted by the same amount as a shift of a threshold voltage, and an effective gate voltage seen from the channel region is brought into a state where it is always kept constant. Further, if the drain voltage and the drain current are constant, a certain amount of hot electron is generated, so that a charge injection speed to the floating gate becomes constant.
This means that in the case where the writing voltage Vpgm and the writing current I are constant, a relation between a shift xcex94Vth of the threshold voltage of the memory transistor and a writing time tw is expressed by a straight line as shown by a 201 of FIG. 2. As a result, in the non-volatile memory of the present invention, by controlling the writing time, it becomes possible to control the threshold voltage with high accuracy.
Incidentally, FIG. 2 also shows a relation between a shift of a threshold voltage in a conventional writing method and a writing time (curve 202 of FIG. 2). In the conventional writing method, in the case where the control gate voltage is made constant, since an effective gate voltage seen from the channel region is decreased as time elapses, a shift amount of threshold voltage is decreased. Thus, it is understood that it is difficult to control the shift of the threshold voltage with high accuracy by controlling the writing time.
In the present invention, the charge injection speed at the time of writing can be optimized by setting the drain voltage and the drain current of the memory transistor to suitable values. Since the writing method of the present invention is the hot electron injection, the drain voltage is required to have such a magnitude as to generate a hot electron. On the other hand, if plenty of hot electrons are generated, since the controllability of charge injection amount is lowered, it is not preferable that the drain voltage is excessively large. It is preferable that the drain voltage of the memory transistor is 3 V or higher though it depends on the size of the memory transistor, and operates in a saturation region relatively close to a linear region. Further, the writing speed is raised by setting the writing voltage Vpgm and the writing current I to large values in such a region, and on the other hand, it becomes possible to suppress consumed current by setting them to small values. With respect to the writing voltage Vpgm and the writing current I, the optimum operation points may be set according to the use of the non-volatile memory.
Besides, since the foregoing writing method is the method of hot electron injection, an electron having energy much higher than an energy barrier due to a tunnel oxide film is mainly concerned. Thus, fluctuation in film quality of the tunnel oxide film hardly influences the injection amount of hot electron, and as compared with the method of charge injection by the FN tunnel current, threshold control having little fluctuation becomes possible.
The non-volatile memory of the present invention uses the foregoing writing operation, so that substantial shortening of a writing time as will be set forth below becomes possible.
First, reference is made to FIG. 3. FIG. 3 qualitatively shows threshold distributions after the conventional writing and the writing of the present invention are carried out without a verify operation, to a memory transistor with the uniform threshold voltages. A distribution 302 expresses a distribution of threshold voltage after the conventional writing, and a distribution 301 expresses a distribution of threshold voltage after the writing of the present invention. Reference character Vtar designates a set threshold voltage after writing. In FIG. 3, when the distribution 302 after the writing of the present invention is compared with the distribution 301 after the conventional writing, both a difference between the center of the distribution and Vtar, and a distribution width are small (xcex94V less than xcex94Vxe2x80x2 and xcex4v less than xcex4vxe2x80x2).
In general, in the case where a difference between threshold voltages expressing different states is small as compared with a distribution width after writing and a distance between centers, since it is impossible to bring all memory cells into the predetermined state by one writing operation, verify writing becomes necessary. On the contrary, in the case where a difference between threshold voltages is larger than a distribution width after writing and a difference between centers, it is possible to carry out writing by one writing operation. Incidentally, the verify writing is a method in which writing is not carried out at one time, but a small amount of writing and readout for confirming a threshold are alternately carried out. This operation is repeated until a threshold reaches a predetermined value.
In the conventional writing method, since the distribution width xcex4vxe2x80x2 after the writing and the difference xcex94Vxe2x80x2 between the centers are large as shown in FIG. 3, the method of verify writing is normally used.
In the case where the writing method of the present invention is used, as shown in FIG. 3, since the distribution width xcex4v after the writing and the difference xcex94V between the centers are small, even in such a difference between threshold voltages that a verify operation is required in the conventional method, it becomes possible to carry out a writing operation in which a verify operation is not carried out. Specifically, in the case where the difference between threshold voltages of different states is larger than the distribution width xcex4v and the difference xcex94V between the centers after the writing of the present invention, the writing operation in which the verify operation is not carried out becomes possible.
Besides, like a multi-value non-volatile memory, in the case where the difference between threshold voltages expressing different states is small, even in the case where the writing method according to the present invention is used, the verify writing becomes necessary. In this case, it is appropriate that the writing operation is constituted by a first writing operation in which the verify operation is not carried out and a second writing operation in which the verify operation is carried out. Specifically, writing into a state slightly lower (approximately xcex4v or xcex94V) than a final threshold voltage is carried out by the first writing operation, and a verify writing operation is carried out for a remaining shortage (approximately xcex4v or xcex94V) of the threshold voltage. Since the amount of writing by the second writing operation is very small, the number of verify times can be greatly decreased as compared with the conventional verify writing.
Thus, in the case where the writing method of the present invention is used, naturally in the writing operation in which the verify operation is not carried out, also in the writing operation in which the verify operation is carried out, the number of verify times can be decreased, and it becomes possible to greatly shorten the writing time.
Besides, in the conventional writing method, as shown in FIG. 2, when the threshold voltage is increased, the charge injection speed is lowered, and the writing operation becomes slow. On the other hand, in the writing method of the present invention, even in a high threshold voltage, the charge injection speed is constant, and the high speed writing operation becomes possible.
The structure of the present invention will be set forth below.
According to the present invention, there is provided an electrically writable and erasable non-volatile memory constituted by a memory element including a charge storage region between an active region and a control gate electrode, characterized in that
an amount of charge injection into the charge storage region is controlled by controlling an amount of current flowing through the memory element and a drain voltage of the memory element.
Further, according to the present invention, there is provided an electrically writable and erasable non-volatile memory constituted by a memory element including a charge storage region between an active region and a control gate electrode, characterized in that
charge injection into the charge storage region is carried out by bringing an amount of current flowing through the memory element and a drain voltage of the memory element into a constant state, and
an amount of charge injection into the charge storage region is controlled by controlling a period of time for a current flows to the memory element.
Further, according to the present invention, there is provided an electrically writable and erasable non-volatile memory including at least a memory cell array in which a plurality of memory cells are arranged in a matrix form and a writing circuit, characterized in that
each of the plurality of memory cells includes a memory element and a selection transistor,
the memory element includes a charge storage region between an active region and a control gate electrode, and
the writing circuit carries out a writing operation by controlling an amount of current flowing through the memory element and a drain voltage of the memory element.
Further, according to the present invention, there is provided an electrically writable and erasable non-volatile memory including at least a memory cell array in which a plurality of memory cells are arranged in a matrix form and a writing circuit, characterized in that
each of the plurality of memory cells includes a memory element and a selection transistor,
the memory element includes a charge storage region between an active region and a control gate electrode,
the writing circuit has a function to hold an amount of current flowing through the memory element and a drain voltage of the memory element constant, and
the writing circuit carries out a writing operation by controlling a period of time for the amount of the current flowing through the memory element and the drain voltage of the memory element are held constant.
Further, according to the present invention, there is provided an electrically writable and erasable non-volatile memory including at least a memory cell array in which a plurality of memory cells are arranged in a matrix form and a writing circuit, characterized in that
each of the plurality of memory cells includes a memory element and a selection transistor,
the memory element includes a charge storage region between an active region and a control gate electrode,
the memory element stores states of k values not less than two values by an erase state having a threshold voltage Vth0, and states having (kxe2x88x921) different threshold voltages Vth1, Vth2, . . . , Vth(kxe2x88x921) higher than the threshold voltage Vth0,
the writing circuit has a function to hold an amount of current flowing through the memory element and a drain voltage of the memory element constant,
the writing circuit carries out a writing operation by controlling a writing time in which the amount of the current flowing through the memory element and the drain voltage of the memory element are held constant; and
ratios between writing times tw1, tw2, . . . , tw(kxe2x88x921) for writing from the erase state to the states having the threshold voltages Vth1, Vth2, . . . , Vth(kxe2x88x921) are tw1:tw2: . . . :tw(kxe2x88x921)=(Vth1xe2x88x92Vth0):(Vth2xe2x88x92Vth0): . . . :(Vth(kxe2x88x921)xe2x88x92Vth0).
Further, the memory element may store multi-value data.
Further, the non-volatile memory may carry out a readout operation by reading a gate voltage of the memory element.
Further, in a writing operation of the non-volatile memory, a verify operation may not be carried out.
Further, the writing operation of the non-volatile memory includes a first writing operation and a second writing operation, and a verify operation is not carried out in the first writing operation while a verify operation may be carried out in the second writing operation.
Further, the memory element constituting the non-volatile memory may be a memory transistor in which a first insulating film, a floating gate electrode constituted by a semiconductor film or a conductive film, a second insulating film, and a control gate electrode are successively stacked on the active region.
The memory element constituting the non-volatile memory may be a memory transistor in which a first insulating film, a cluster layer which includes clusters made of semiconductor or conductor as charge-trapped centers, a second insulating film, and a control gate electrode are successively stacked on the active region.
The memory element constituting the non-volatile memory may be a memory transistor of MNOS structure or MONOS structure.
Further, there is provided a semiconductor device characterized in that the non-volatile memory is used as a recording medium.
Further, there is provided a microprocessor as the semiconductor device.
Further, there is provided a display, a video camera a goggle display, a DVD player, a head mount display, a personal computer, a portable telephone, or a car audio, as the semiconductor device.